At least some example embodiments of the inventive concepts relate to a data processing circuit, and more particularly, to a data processing circuit for independently controlling a sampling point with respect to data and a data processing system including the same.
A semiconductor memory device which supports a dual data rate (DDR) operation uses a data strobe signal for transmitting data. In a DDR method, data is transmitted in response to a rising edge and a falling edge of the data strobe signal, such that a data transmission frequency twice that of a frequency of a clock signal can be achieved.
A duty cycle is a percentage of a period of time in which a signal is high with respect to the period of one cycle of a pulse. When the duty cycle of a clock signal deviates from 50%, a width of a data cycle output at a rising edge of the clock signal and a width of a data cycle output at a falling edge thereof vary, such that the margin of a data valid window is reduced and stability of a system is deteriorated.
A system including a semiconductor memory device improves the margin of a data valid window by directly changing a duty cycle using a duty adjusting circuit. In addition, the duty adjusting circuit needs an additional compensation circuit for compensating variations in process, voltage, and temperature (PVT).